LAYOUT STRUCTURE FOR DYNAMIC RANDOM ACCESS MEMORY DEVICE

摘要

PURPOSE: A layout structure of a dynamic random access memory(DRAM) unit is provided to reduce chip size, improve process margin and expand metal line space by continuously forming active region required to provide bit line equalizing voltage. CONSTITUTION: An active region(100) is located between array regions(10) and bit line equalizing regions(200) in vertical directions with the bit line equalizing regions(200). The active region(100) is formed on the main surface of a semiconductor plate electrically connected to the bit line equalizing regions(200). A metal-active contact(102) is formed at the crosslink region of the active region(100) and the bit line equalizing regions(200) to electrically connect the bit line equalizing regions(200) with the active region(100).