发明名称 Memory apparatus
摘要 A memory chip includes a main memory cell; a row-wise redundant memory cell and a column-wise redundant memory cell for relieving a defect existing in the main memory; an identification number designation terminal for storing an identification number corresponding to the main memory cell; an address terminal for receiving the identification number; and a redundant row selector circuit and a redundant column selector circuit for performing allocation so as to replace a defective memory space of the main memory cell with a memory space of the redundant memory cells. The redundant selector circuits allocate a memory space corresponding to the defect of the main memory cell to the redundant memory cells when the identification number received from the address terminal coincides with the identification number of the identification number specification terminal.
申请公布号 US7272057(B2) 申请公布日期 2007.09.18
申请号 US20040573460 申请日期 2004.09.24
申请人 SHARP KABUSHIKI KAISHA 发明人 SATO TOMOTOSHI
分类号 G01R31/28;G11C29/00;G11C29/04 主分类号 G01R31/28
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