DATA WRITING SYSTEM FROM ASYNCHRONOUS DATA BUS TO REGISTER

摘要

PROBLEM TO BE SOLVED: To eliminate the competition between data write to a master registration and data transfer from the master register to a slave register and to prevent a malfunction. SOLUTION: Data from an asynchronous data bus 4 is written to a master register 1 according to the fall of a write signal S2 given as asynchronous with a timer clock S1. On the other hand, data written to the register 1 at every rise of a load signal S8 that is given while synchronized with the clock S1 is transferred to a slave register 2. In such a case, the load signal S8 is prohibited from being generated for the period of the signal S2 from rise to fall and for a prescribed period from the fall.