Tuning gate lengths in semiconductor device structures

摘要

A method for tuning gate lengths in nanowire semiconductor device structures. The present invention tunes the gate length by having the suspension height of the nanowire channels altered. The first method alters the suspension height by offsetting the height of the nanowires while utilizing gates of similar tapered dimensions, such that the nanowires pass through the gate regions at different heights and result in different gate length nanowire transistor device structures. The second method alters the suspension height by offsetting the height of the steps that the gates of similar tapered dimensions are formed on, such that the nanowires pass through the gate regions at different heights, resulting in different gate length nanowire transistor device structures. Both methods facilitate a decrease in overall fabrication costs by allowing the same type of patterned gate stacks to be used in order to produce channels of various lengths.

主权项

1. A method for modulating a plurality of gate lengths of a nanowire transistor device structures, the method comprising:
providing a first stack of materials and a second stack of materials, wherein each stack of materials comprises a substrate layer, an insulator layer disposed on the substrate layer, and a sacrificial layer disposed on the insulator layer; removing a portion of the sacrificial layer of only the first stack of materials to form a partially recessed surface within the sacrificial layer, wherein a depth that the partially recessed surface is etched to determines a channel length; forming, on the sacrificial layer of the first stack of materials and the second stack of materials, a semiconductor layer having an upper section on the second stack of materials and a recessed section on the first stack of materials; removing portions of the semiconductor layer on the first stack of materials and the second stack of materials to form crossing sections and a plurality of depressed regions; removing portions of the sacrificial layer under the semiconductor layer of the first stack of materials and the second stack of materials to form undercuts; forming nanowires from the crossing sections of the semiconductor layer; and patterning tapered gate stacks within the undercuts such that the tapered gate stacks are disposed around a portion of the nanowires.