发明名称 Hybrid hardware and software implementation of transactional memory access
摘要 Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
申请公布号 US9529715(B2) 申请公布日期 2016.12.27
申请号 US201313843890 申请日期 2013.03.15
申请人 Intel Corporation 发明人 Kumar Sanjeev;Hughes Christopher J.;Kundu Partha;Nguyen Anthony
分类号 G06F12/08;G06F9/46;G06F9/52;G06F9/30;G06F9/38 主分类号 G06F12/08
代理机构 Nicholson De Vos Webster & Elliott LLP 代理人 Nicholson De Vos Webster & Elliott LLP
主权项 1. An apparatus comprising: a processor including a transactional cache and a regular cache, wherein both caches are physically located within the processor; and a policy manager to select, upon beginning a transaction after detecting an exception, a first mode or a second mode to implement transactional memory accesses, wherein executed memory operations of the transaction in either the first and second mode are not committed until all read and write memory operations of the transaction have completed execution; wherein, in the first mode, the transactional cache is utilized to perform all read and write memory operations and, in the second mode, only memory operations explicitly specified as transactional are a part of the transaction and wherein the regular cache is utilized to perform read and write memory operations of the transaction in the second mode.
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