发明名称 FLOATING POINT MULTIPLIER
摘要 PURPOSE:To perform the multiplication of floating points at a high speed by using the carry signal received from a carry detector to perform the shift operations of a mantissa part and the control of the increment process of an exponent part and carrying out both rounding and exceptional processes in parallel with each other. CONSTITUTION:A floating point multiplier fetches the output data received from a fixed point multiplication circuit 10 and the rounding signal RD produced by a rounding process control circuit 17 to detects whether an overflow occurs in a rounding process or not. If so, a carry detector 15 sets the carry signal CO at 1. The signal CO is inputted to a shifter 19 of a mantissa part and a multiplexer 24 of an exponent part for control of the shift process carried out after the rounding process of the mantissa part and the increment process of the exponent part. The rounding and exceptional processes can be performed in parallel with each other with use of the detector 15. Then the critical paths are set as 10 15 24 40 42. Thus the computing speed is increased for a floating point multiplier.
申请公布号 JPH02183828(A) 申请公布日期 1990.07.18
申请号 JP19890004399 申请日期 1989.01.11
申请人 FUJITSU LTD 发明人 KATSUNO AKIRA
分类号 G06F7/38;G06F7/487;G06F7/507;G06F7/52;G06F7/53 主分类号 G06F7/38
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