| 摘要 |
A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined that the carry does not pass through any of the adder blocks, the calculating unit is clocked with a clock period, which is sufficient that the carry passes almost fully through an adder block, and passes through at least part of the upstream adder block. If it is determined, that the carry passes fully through an adder block, a panic signal is generated. The adder block is decelerated, so that the clock period is high enough that the carry additionally fully passes through another adder block. Only in a case of panic signals of two adjacent adder blocks, is the calculating unit is decreased so much, that the carry passes from the least significant digit of the calculating unit to the most significant digit of the calculating unit.
|
