| 摘要 |
A three-state buffer circuit has a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage. An output signal is outputted from a node between these pull-up side transistor and the pull-down side transistor. A first level shift circuit is connected to a gate of the pull-up side transistor, and a voltage of a data signal is converted from an internal power supply potential lower than an external power supply potential to the external power supply potential. A second level shift circuit is connected to a gate of the pull-down side transistor, and a voltage of a data signal is converted from the internal power supply potential to the external power supply potential. Then, when a change of the data signal read out from a memory cell is detected, the detected signal is delayed, and a control signal for controlling an output of an output circuit to be active or inactive is outputted to a first level shift circuitry and a second level shift circuitry. When the control signal is in a first state (grounding), either the pull-up side transistor or pull-down side transistor is turned OFF, and the output terminal enters a high impedance. When the control signal is in a second state, a signal according to "high" or "low" of the data signal is outputted to the output terminal.
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