Detection of hardware errors using redundant transactions for system test

摘要

A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, synchronizing the transaction on the cores, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

主权项

1. A method for detecting errors in hardware, the method comprising:
running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction; periodically synchronizing the transaction on the cores; and comparing results of the transaction on the cores; determining an error in one or more of the cores; wherein synchronizing the transaction further comprises: suspending the transaction running on each of the cores at a same instruction; reading an address of a modified cache line in a transactional store of a first core of the plurality of cores; writing the address and a value at the address as first data to a common memory area shared by the cores; writing data from registers of the first core to the common memory area; and sending a bus transaction including a pointer to the common memory area to a second core of the plurality of cores.