| 摘要 |
<p>PURPOSE:To reduce a clock skew after a lay-out by varying the output driving capability of a clock driver circuit in each clock line. CONSTITUTION:The clock waveform of a sampling clock 9 is inputted to a monitor flip flop F/F 3, and transmitted to a monitor circuit 5. A control circuit 4 controls the skew of a clock wiring 6 so as to be the minimum by the output of the monitor circuit 5 and an outside control signal 7, so that the driving capacity of each clock driver circuit 1 can be varied. Thus, the difference of the influence of each adjacent and crossing clock wiring after the lay-out can be reduced.</p> |
