发明名称 |
Cascode amplifier |
摘要 |
In one embodiment, a cascode amplifier includes an amplifier circuit, a replica circuit, a bias circuit, and a feedback circuit. The amplifier circuit includes a first transistor and a second transistor. The second transistor is cascode-connected to the first transistor. The replica circuit includes a third transistor and a fourth transistor. The third transistor has a control terminal connected to a control terminal of the first transistor. The fourth transistor is cascode-connected to the third transistor. The bias circuit applies a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor. The feedback circuit performs a feedback control of a voltage of the control terminal of the third transistor. The feedback circuit reduces the difference between a reference current and a current at a predetermined point of the replica circuit. |
申请公布号 |
US9438175(B2) |
申请公布日期 |
2016.09.06 |
申请号 |
US201414487465 |
申请日期 |
2014.09.16 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
Onizuka Kohei |
分类号 |
H03F3/04;H03F1/22;H03F1/30;H03F1/32 |
主分类号 |
H03F3/04 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A cascode amplifier comprising:
an amplifier circuit including a first transistor and a second transistor cascode-connected to the first transistor; a replica circuit including a third transistor having a control terminal connected to a control terminal of the first transistor, and a fourth transistor cascode-connected to the third transistor; a bias circuit applying a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor; and a feedback circuit performing a feedback control of a voltage of the control terminal of the third transistor to reduce the difference between a reference current and a current at a predetermined point of the replica circuit, wherein a ratio of a ratio of a channel width to a channel length of the third transistor to a ratio of a channel width to a channel length of the fourth transistor is equal to a ratio of a ratio of a channel width to a channel length of the first transistor to a ratio of a channel width to a channel length of the second transistor. |
地址 |
Minato-ku JP |