发明名称 |
Voltage-controlled delay line, direct phase controlled voltage-controlled oscillator, clock/data recovery circuit, and clock/data recovery apparatus |
摘要 |
A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.
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申请公布号 |
US6166572(A) |
申请公布日期 |
2000.12.26 |
申请号 |
US19980040451 |
申请日期 |
1998.03.18 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
YAMAOKA, NOBUSUKE |
分类号 |
H03K3/354;H03K5/00;H03K5/13;H03L7/07;H03L7/081;H03L7/099;H04L7/02;H04L7/033;(IPC1-7):H03L7/07 |
主分类号 |
H03K3/354 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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