发明名称
摘要 <p>A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which case a device code indicating that the EPROM is a 2M bit EPROM is read out from the 2M code memory line (2a). When a defective portion is present in one of the first and the second data memory regions (1a, 1b), the EPROM may be used as a 1M bit EPROM, in which case a device code indicating that the EPROM is a 1M bit EPROM is read out from the 1M code memory line (2b).</p>
申请公布号 JPH0793037(B2) 申请公布日期 1995.10.09
申请号 JP19880293964 申请日期 1988.11.21
申请人 发明人
分类号 G11C16/02;G11C17/00;G11C29/00;G11C29/04;(IPC1-7):G11C29/00;G11C16/06 主分类号 G11C16/02
代理机构 代理人
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