Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers

摘要

This invention is a process for fabricating ultra-large-scale integration CMOS circuits using a single polysilicon gate layer for both N-channel and P-channel devices, a single mask step for defining the gates of both N-channel and P-channel devices, the fabrication of one set of disposable spacers for N-channel implants, and the fabrication of another set of disposable spacers for P-channel source/drain implants. The set of spacers used for P-channel implants also comprises material deposited to fabricate the spacers for the N-channel implants. The process is adaptable to LDD structures for both N-channel and P-channel devices or for only N-channel devices. The process is also compatible with anti-punchthrough implants for both types of devices.