Optical transceiver including separate signal lines in addition to an SPI bus between a processor device and a logic device

摘要

A compact optical transceiver is provided by using a serial communication bus as a communication bus connecting a logic device and a microcomputer. This optical transceiver is connected through an MDIO bus to an external upper layer and is provided with a microcomputer, a logic device, the MDIO bus, a serial communication bus, and a first dedicated signal line. The microcomputer has an MDIO register. The logic device receives a command code, address information, and a single data block from the upper layer through the MDIO bus, transmits the address information and the single data block to the microcomputer through the serial communication bus, and transmits the OP code to the microcomputer through the first dedicated signal line.

主权项

1. An optical transceiver to communicate with an external upper layer through a management data input/output (MDIO) bus, the optical transceiver comprising:
a microprocessor configured to monitor and control an internal state of the optical transceiver, the microprocessor including a transmission register, a reception register, an address register, and a plurality of MDIO registers, the address register specifying one of the MDIO registers as a current register, the transmission register being configured to store a single data block transferred from the current register every time the address register or the current register is updated; a logic device configured to receive first serial data and second serial data from the upper layer through the MDIO bus and convert the first serial data to first parallel data, the second serial data coming after the first serial data; a serial peripheral interface (SPI) bus configured to send the second serial data from the logic device to the reception register and to send the single data block from the transmission register to the logic device; and two digital signal lines configured to send the first parallel data from the logic device to the microprocessor in parallel with the SPI bus, wherein the second serial data is sent from the logic device to the microprocessor through the SPI bus after the first parallel data is sent from the logic device to the microprocessor through the two digital signal lines, and wherein the single data block is stored in the transmission register before the microprocessor receives next first serial data that follows the first serial data.