| 摘要 |
A circuit for protecting nonvolatile memories against loss of Vcc while Vpp is high. An NMOS gated by Vcc is connected, in series with a load element, between Vpp and ground. The node between the NMOS and the load element gates a PMOS which is interposed between Vpp and the memory. Thus when Vcc fails while Vpp is high, the NMOS will turn off, and the load element will pull up the gate of the PMOS to turn it off, interrupting the Vpp supply. This prevents spurious write or erase operations under these circumstances. The circuit can be designed to trigger at threshold voltages as low as VTN, and is thus particularly advantageous for operation with specified Vcc values of 3 Volts or less.
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