发明名称 Chip mode isolation and cross-talk reduction through buried metal layers and through-vias
摘要 A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.
申请公布号 US9397283(B2) 申请公布日期 2016.07.19
申请号 US201514610411 申请日期 2015.01.30
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Abraham David W.;Keefe George A.;Lavoie Christian;Rothwell Mary E.
分类号 H01L39/04;H01L27/18;H01L39/24;H01L39/22;B82Y10/00;G06N99/00;H01L23/538 主分类号 H01L39/04
代理机构 Cantor Colburn LLP 代理人 Cantor Colburn LLP ;Alexanian Vazken
主权项 1. A chip surface base device, comprising: a first substrate; a plurality of vias formed in the first substrate, wherein the plurality of vias is etched into a surface of the first substrate; metal fillings deposited into the plurality of vias; a second substrate bonded with the first substrate, wherein the metal fillings are exposed, wherein the second substrate is bonded with the first substrate includes a metal layer between the second substrate and the first substrate; a qubit circuit, wherein the qubit circuit is on the first substrate and is coupled to a plurality of chip modes, the plurality of chip modes operative to conduct into the metal fillings deposited into the plurality of vias and define a short into the metal layer between the second substrate and the first substrate, wherein the plurality of chip modes have wavelengths longer than distances between vias in the plurality of vias; and wherein the plurality of vias is arranged in a location on the first substrate such that the plurality of vias isolates the plurality of chip modes between the plurality of vias and the metal layer between the second substrate and the first substrate.
地址 Armonk NY US