发明名称 APPARATUS CAPABLE OF ESTIMATING RESISTANCE PROPERTY
摘要 <P>PROBLEM TO BE SOLVED: To easily and correctly estimate breakage of a chip due to impact force in bonding after stacking chips, when a fragile porous low-k material which has less bondability and is easily peeled is used as an insulating film and in a thin chip having a chip thickness of 100 &mu;m or less. <P>SOLUTION: In an apparatus capable of estimating stack resistance by stacking to bond a chip B (upper chip) onto a chip A (lower chip); an element for evaluating the resistance is provided on the chip A, and the chip positions correspond to corners in a stacking range within a stacking range of the chips A and B and in a region inside of 50-1,000 &mu;m from the outermost peripheral edge of the stacking range. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007194531(A) 申请公布日期 2007.08.02
申请号 JP20060013439 申请日期 2006.01.23
申请人 CONSORTIUM FOR ADVANCED SEMICONDUCTOR MATERIALS &RELATED TECHNOLOGIES 发明人 ISHIZAWA HIDEAKI
分类号 H01L21/60;H01L21/3205;H01L21/66;H01L23/52 主分类号 H01L21/60
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