REMOTE BIST FOR HIGH SPEED TEST AND REDUNDANCY CALCULATION

摘要

Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and. local higher-speed executable instructions. A standalone BIST logic controller (110) operates at a lower frequency and communicates with a plurality of embedded memory arrays (111-113) using a BIST instruction. set. A block of higher-speed test logic (116) is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller (110) at a higher frequency. The higher-speed test logic includes a multiplier (118) for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller (110) enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.