Dual-rail encoding

摘要

Embodiments may include a method, system and apparatus for providing for encoded dual-rail signal communications in asynchronous circuitry. A dual rail signal pair is received. The dual rail signal pair comprises a first value indicative of a first wait state, a second value indicative of a logic value of a first bit, a third value indicative of a second wait state and a first logic value of a second bit, and/or a fourth value indicative of second wait state and a second logic value of said second bit.

主权项

1. A method comprising:
receiving, at an encoder, a first signal representing a first bit; receiving, at the encoder, a second signal representing a second bit; encoding, at the encoder, said first and second bits into a first dual-rail signal that spans first, second, and third time periods, wherein said dual-rail signal comprises: a two-bit representation of a first wait state during said first time period; a two-bit representation of said first bit during said second time period; and a two-bit representation of both a second wait state and said second bit during said third time period; and providing said first dual-rail signal from the encoder to a dual-rail receiver via a first wire pair.