| 摘要 |
A capacitor structure for an integrated circuit, the structure including a main capacitor and a parasitic capacitor, comprising: a substrate (2000) of a first conductivity type; a first dielectric layer (2040); a first conductive layer (2010) disposed over the first dielectric layer (2040), said first conductive layer (2010) forming a first plate of the main capacitor and a first plate of the parasitic capacitor; a second dielectric layer (2020) disposed over the first conductive layer (2010); and a second conductive layer (2030) disposed over the second dielectric layer (2020), the second conductive layer (2030) forming a second plate of the main capacitor; characterised in that the capacitor structure further comprises a well (2100) disposed within the substrate (2000) which is of a second conductivity type opposite to said first type, the first dielectric layer (2040) is disposed over the well (2100) and the well (2100) forms a second plate of the parasitic capacitor and a further, junction cacapitor with the substrate (2000), the configuration being such that the parasitic and junction capacitors are mutually in series and in series with the main capacitor such as to reduce stray capacitance.
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