发明名称 Shift amount floating-point calculating circuit with a small amount of hardware and rapidly operable.
摘要 <p>In a floating-point arithmetic unit for performing floating-point arithmetic of first and second input data which are represented by a floating-point representation and composed of first and second exponent parts and first and second mantissa parts, a shift amount calculating circuit comprises first and second subtracters (26, 27) supplied with lower (n + 1) bits of the first and the second exponent parts. The first subtracter subtracts a first lower number (#EA1) from a second lower number (#EB1) to produce a first difference signal (RS1). The second subtracter subtracts the second lower number (#EB1) from the first lower number (#EA1) to produce a second difference signal (RS1). Supplied with the first and the second exponent parts, an exponent comparing unit (28) compares the first exponent part with the second exponent part to produce a comparison result signal (CP1, CP2, CP3, CP4). Responsive to the comparison result signal, a first selector (31) selects one of the first difference signal and first and second value signals ("0", "64") as a first right-shift amount signal (SD1). Responsive to the comparison result signal, a second selector (32) selects one of the second difference signal and the first and the second value signals as a second right-shift amount signal (SD2). &lt;IMAGE&gt;</p>
申请公布号 EP0474247(A2) 申请公布日期 1992.03.11
申请号 EP19910115107 申请日期 1991.09.06
申请人 NEC CORPORATION 发明人 ISHIHARA, SHINGO
分类号 G06F5/01;G06F7/485;G06F7/50 主分类号 G06F5/01
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