发明名称
摘要 PURPOSE:To shorten each pitch between memory cells and between sense amplifiers by forming the other of signal conductors such as adjacent bit lines onto an insulating layer coating one of the signal conductors. CONSTITUTION:A layer insulating film 212 is shaped onto a bit line 103 in memory cells 214 forming a row, the line 103 for the memory cell 214 and an adjacent bit line 104 in adjacent rows are shaped onto the film 212, and insulation between the lines 103 and 104 is ensured excellently even when a conductor spacing is shortened. Accordingly, both pitches among the cells 214 and pitches among sense amplifiers with said pitches can be reduced, thus realizing a semiconductor memory storage in a high-density half memory cell array.
申请公布号 JPH07120755(B2) 申请公布日期 1995.12.20
申请号 JP19860254308 申请日期 1986.10.24
申请人 发明人
分类号 H01L21/3205;G11C11/401;H01L21/8242;H01L23/52;H01L27/10;H01L27/108;(IPC1-7):H01L27/108;H01L21/320;H01L21/824 主分类号 H01L21/3205
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