| 摘要 |
PURPOSE: A digital signal processor is provided to rapidly process signals by simultaneously performing a rounding of data in case that the saturation process of the data are performed, and by removing the time for processing the rounding of the data. CONSTITUTION: The first register(30) inputs N-bit data from the first external bus(31). The first and the second bit alignment device(32, 34) shift the N-bit data inputted from the first register from N-bit to N+r bit(30). The first multiplexer(36) provides N+r bit data on the first input port or the second input port to the first guard bit adder(38). The second register(40) temporarily stores N-bit data inputted via the first external bus(31). The second multiplexer(42) provides N-bit data from the first external bus(31) provided to the first input port(39) to the third register(44). The third register(44) temporarily stores N-bit data from the second multiplexer(42). A multiplier(46) multiplies data stored in the second and the third register(40, 44). A wiring adjuster(50) connected between the fourth register(48) and the second external bus(37) converts 2N-bit data stored in the fourth register(48) into N+r bit data. The third multiplexer(52) or the fifth multiplexer(56) is equipped in the first internal bus(35). A barrel shifter(60) performs a scaling of logic values of data from the fifth multiplexer(56). The barrel shifter(60) is connected with the first ALU(Arithmetic Logic Unit)(58) in parallel. A rounding/saturation processor(86) selects N-bit data from the r+1th lower bit among g+N+r bit data from the tenth multiplexer(80). The rounding/saturation processor(86) performs the rounding of g+N+r bit data from the tenth multiplexer(80).
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