发明名称 |
Method and pattern for avoiding micro-loading effect in an etching process |
摘要 |
A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.
|
申请公布号 |
US6150678(A) |
申请公布日期 |
2000.11.21 |
申请号 |
US19990248582 |
申请日期 |
1999.02.11 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
TUNG, CHIA-CHING;LU, CHENG-LUNG;LUO, HUNG-YI |
分类号 |
H01L21/311;H01L21/768;H01L23/528;(IPC1-7):H01L27/10 |
主分类号 |
H01L21/311 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|