DUAL EVENT COMMAND

摘要

A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

主权项

1. A method of operating a memory device, the method comprising:
receiving a memory command within two clock cycles, wherein the two clock cycles comprise a first pulse and a second pulse consecutively following the first pulse, wherein each of the first and second pulses includes a first edge and a second edge, wherein the memory command includes a command and an address, wherein the address includes a first portion and a second portion, wherein the memory device includes a set of first pins and a set of second pins, and wherein the receiving the memory command comprises:
receiving the command at the set of first pins and the first portion of the address at the set of second pins in relation to the first edge of the first pulse of the two clock cycles; andreceiving the second portion of the address at the set of second pins in relation to the first edge of the second clock of the two clock cycles while one of the set of first pins is being supplied with a fixed logical level.