发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
摘要 |
<P>PROBLEM TO BE SOLVED: To increase the operation speed of a semiconductor memory including an ECC circuit. Ž<P>SOLUTION: A read signal RYPA to control the operation timing of a read latch circuit 101 is input to a read latch circuit 101 and also to an ECC replica circuit 105. The signal is input to a write-buffer circuit 104 as a write signal WYPA at a timing delayed by the time corresponding to the signal propagation time through the circuit corresponding to the signal propagation path in an ECC circuit 102. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
申请公布号 |
JP2010020839(A) |
申请公布日期 |
2010.01.28 |
申请号 |
JP20080180388 |
申请日期 |
2008.07.10 |
申请人 |
PANASONIC CORP |
发明人 |
NAKAMURA TOSHIHIRO;IIDA MASAHISA |
分类号 |
G11C29/42;G11C11/401;G11C11/413 |
主分类号 |
G11C29/42 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|