HIGH SPEED CYCLICAL REDUNDANCY CHECK SYSTEM USING A PROGRAMMABLE ARCHITECTURE
摘要
A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.
申请公布号
EP0830741(A1)
申请公布日期
1998.03.25
申请号
EP19950944609
申请日期
1995.12.08
申请人
MICRON TECHNOLOGY, INC.;MICRON TECHNOLOGY, INC.
发明人
THOMANN, MARK, R.;VO, HUY, THANH;INGALLS, CHARLES, L.