Array substrate and a display device

摘要

An array substrate comprises a plurality of subpixels, each of the subpixels comprising: at least one thin film transistor, an organic resin layer, and uncontacted first pixel electrode and second pixel electrode arranged along the data line direction; the first pixel electrode extends to the above of a first gate line, the second pixel electrode extends to the above of a second gate line, the first gate line and the second gate line are adjacent to each other; the first pixel electrodes of two adjacent subpixels located at two sides of the first gate line are connected above the first gate line, the second pixel electrodes of two adjacent subpixels located at two sides of the second gate line are connected above the second gate line.

主权项

1. An array substrate, comprising; a plurality of subpixels, each of the subpixels being defined by intersection of two adjacent gate lines and two adjacent data lines, wherein each of the subpixels comprising comprises: at least one thin film transistor, a organic resin layer located above the thin film transistor, and a first pixel electrode and a second pixel electrode located above the organic resin layer and arranged along the data line direction; wherein the first pixel electrode and the second pixel electrode are out of contact; wherein the first pixel electrode extends to the above of a first gate line that is close to the first pixel electrode, the second pixel electrode extends to the above of a second gate line that is close to the second pixel electrode; wherein the first gate line and the second gate line are adjacent to each other; wherein along the data line direction and between any two adjacent data lines, the first pixel electrodes of two adjacent subpixels located at two sides of the first gate line are both close to the first gate line and are connected above the first gate line, the second pixel electrodes of two adjacent subpixels located at two sides of the first gate line are both away from the first gate line; wherein along the data line direction and between any two adjacent data lines, the second pixel electrodes of two adjacent subpixels located at two sides of the second gate line are both close to the second gate line and are connected above the second gate line, the first pixel electrodes of two adjacent subpixels located at two sides of the second gate line are both away from the second gate line; and wherein the first pixel electrodes of two adjacent subpixels at two sides of the first gate line are electrically connected with the drain of at least one thin film transistor, the second pixel electrodes of two adjacent subpixels at two sides of the second gate line are electrically connected with the drain of at least one thin film transistor.