Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

摘要

Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.

主权项

1. A method, comprising:
receiving, at a semiconductor device to be tested, an external test clock signal, wherein the external test clock signal includes a first set of external test clock pulses; determining, using the external test clock signal, a first pulse count value representing the first set of external test clock pulses; causing the semiconductor device to generate a first set of higher frequency test clock signals for a first configurable number of clock cycles during a first capture period, wherein the first configurable number of clock cycles corresponds to the first pulse count value; generating at the semiconductor device an on-chip clock (OCC) Clock Chain signal, the OCC Clock Chain signal including a first set of OCC Clock Chain data represented by a first set of bits; determining, using the OCC Clock Chain signal, an OCC pulse count value representing a specific number of higher frequency test clock signal(s) to be generated at the semiconductor device during a second capture period; and causing the semiconductor device to generate a second set of higher frequency test clock signals for a second configurable number of clock cycles during the second capture period, wherein the second configurable number of clock cycles corresponds to the OCC pulse count value.