| 摘要 |
A processor architecture arrangement for emulated shared memory (ESM) architectures, comprising a number of multi-threaded processors each provided with interleaved inter-thread pipeline (400) and a plurality of functional units (402, 402b, 402c, 404, 404b, 404c) for carrying out arithmetic and logical operations on data, wherein the pipeline (400) comprises at least two operatively parallel pipeline branches (414, 416), first pipeline branch (414) comprising a first sub-group of said plurality of functional units (402, 402b, 402c), such as ALUs (arithmetic logic unit), arranged for carrying out integer operations, and second pipeline branch (416) comprising a second, non-overlapping sub-group of said plurality of functional units (404, 404b, 404c), such as FPUs (floating point unit), arranged for carrying out floating point operations, and further wherein one or more of the functional units (404b) of at least said second sub-group arranged for floating point operations are located operatively in parallel with the memory access segment (412, 412a) of the pipeline (400). |
| 主权项 |
1. A processor architecture arrangement for emulated shared memory (ESM) architectures, comprising;
a number of multi-threaded processors each provided with a interleaved inter-thread pipeline and a plurality of functional units for carrying out arithmetic and logical operations on data, wherein the interleaved inter-thread pipeline includes at least two operatively parallel pipeline branches a first pipeline branch having a first sub-group of said plurality of functional units which are arranged for carrying out integer operations, and a second pipeline branch having a second, non-overlapping, sub-group of said plurality of functional units arranged for carrying out floating point operations, and wherein at least one of the functional units of the second sub-group which is arranged for floating point operations is located operatively in parallel with a memory access segment of the pipeline. |
