发明名称 PROTECTION CIRCUIT FOR PREVENTING AN OVER-CURRENT FROM AN OUTPUT STAGE
摘要 A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node.
申请公布号 US2016308352(A1) 申请公布日期 2016.10.20
申请号 US201514685611 申请日期 2015.04.14
申请人 Elite Semiconductor Memory Technology Inc. 发明人 Tsao Szu-Chun
分类号 H02H9/02 主分类号 H02H9/02
代理机构 代理人
主权项 1. A semiconductor device, comprising: an output stage, comprising a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, comprising a first voltage clamping circuit, comprising a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are arranged to clamp a gate voltage of the PMOS of the output stage and are connected in series between the first supply voltage and a gate terminal of the PMOS, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor, and the first switch is arranged to selectively couple the first supply voltage to the node between the first transistor and the second transistor.
地址 Hsinchu TW