Array substrate and display device

摘要

An array substrate and a display device that comprises the array substrate are disclosed. The array substrate comprises a base substrate, a plurality of scan lines (Ga, 21) and a plurality of data lines (Dr, 4) that are provided on the base substrate and intersect with each other, and a plurality of sub-pixel regions arranged evenly; sub-pixel regions in two adjacent rows are configured as one pixel row group, so that a plurality of pixel row groups are arranged longitudinally, and between two rows of sub-pixel regions within each of the pixel row groups and/or between every two adjacent pixel row groups, there are provided two scan lines (Ga, 21), which overlap in partial (22b) and are insulated from each other; or, sub-pixel regions in two adjacent columns are configured as one pixel column group, so that a plurality of pixel column groups are arranged transversely, and between two columns of sub-pixel regions within each of the pixel column groups or between every two adjacent pixel column groups, there are provided two data lines (Dr), which overlap in partial and are insulated from each other. The array substrate has a relatively high aperture ratio.

主权项

1. An array substrate, comprising a base substrate, a plurality of scan lines and a plurality of data lines that are provided on the base substrate and intersect with each other, and a plurality of sub-pixel regions arranged evenly, each of which comprises one thin film transistor, wherein
sub-pixel regions in two adjacent rows are configured as one pixel row group, so that a plurality of pixel row groups are arranged longitudinally, and two scan lines are provided in at least one of Position A and Position B, Position A being between two rows of sub-pixel regions within each of the pixel row groups, Position B being between every two adjacent pixel row groups, each of which is electrically connected to gate electrodes of thin film transistors within one of sub-pixel regions of the two rows of sub-pixel regions that are adjacent to them, respectively, and these two scan lines overlap in partial and are insulated from each other; wherein each of the sub-pixel regions further includes a pixel electrode; the two scan lines are a first scan line and a second scan line, respectively; the first scan line and gate electrodes of thin film transistors corresponding to the first scan line are located in a same layer; the second scan line comprises at least one overlapping section and at least one non-overlapping section; the overlapping section is a portion of the second scan line that overlaps the first scan line, and the overlapping section and a data line or the pixel electrode are located in a same layer; the non-overlapping section is a portion of the second scan line that does not overlap the first scan line, and is electrically connected to a gate electrode of a thin film transistor corresponding to the second scan line, and the non-overlapping section and the gate electrode of the thin film transistor corresponding to the second scan line are located in a same layer; the overlapping section and the non-overlapping section of the second scan line are electrically connected so as to provide a continuous scan line capable of transmitting signals.