Integrated Circuit Including a Programmable Logic Analyzer with Enhanced and Debugging Capabilities and a Method Therefor

摘要

A system including an embedded logic analyzer block having an input receiving a plurality of signals from a system under test, and a trigger event block detecting an occurrence of an event based in part upon the plurality of signals. The system further includes a block with a first input receiving one or more of the plurality of signals, a second input receiving a signal based upon the detection of the occurrence of the event, circuitry generating a distinct set test signals based on the signals at the first input and second input of the block, the distinct set of test signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block, and an output providing the generated distinct set of test signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering.

主权项

1. A system, comprising:
an integrated circuit, comprising:
an embedded logic analyzer block having an input for receiving a plurality of signals from one or more portions of a system under test for sampling and event triggering, and a trigger event block configurable to detect an occurrence of an event based in part upon the plurality of signals; anda block having a first input coupled to the embedded logic analyzer block for receiving therefrom one or more of the plurality of signals, a second input coupled to the trigger event block for receiving therefrom a signal based upon the detection of the occurrence of the event, circuitry generating a distinct set of one or more test signals based on the signals at the first input and second input of the block, the distinct set of one or more test signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block and from the one or more of the plurality of signals received at the first input of the block, and an output for providing the generated distinct set of one or more test signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering.