发明名称 CONNECTING DEVICE, IDDQ TEST METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>A tester board (1) is provided with a test circuit (11). The test circuit is provided with a first switch (13) and a second switch (14), which are inserted in series into a path connecting a power supply terminal (4) with a semiconductor device (2). Furthermore, the test circuit is provided with a first capacitive element (15) connected between the first switch and the second switch; a second capacitive element (16) connected with a path connecting the second switch with the semiconductor device; a resistive element (18) connected with the second switch in parallel; and an amplifier (17) for amplifying a potential difference between potentials on both ends of the resistive element. In a status where the first switch and the second switch are turned on, the first capacitive element and the second capacitive element are charged by power supplied from the power supply terminal. When the first switch and the second switch transit into an off-status, a current flows from the first capacitive element to the semiconductor device by charge redistribution. Whether there is current leakage caused by a defect is detected by the level of the potential difference formed by the current, between the potentials on the both ends of the resistive element.</p>
申请公布号 WO2007049331(A1) 申请公布日期 2007.05.03
申请号 WO2005JP19541 申请日期 2005.10.25
申请人 RENESAS TECHNOLOGY CORP.;OZAKI, HIROSHI;KURAISHI, TAKASHI 发明人 OZAKI, HIROSHI;KURAISHI, TAKASHI
分类号 G01R31/26 主分类号 G01R31/26
代理机构 代理人
主权项
地址