| 摘要 |
PURPOSE: To provide a generalized and hypercube topology having superior connectivity, a high band performance and a low waiting time on a processor having parallel architectures realizing a high output processing through the use of multiple central processing units CPU. CONSTITUTION: The processor is provided with plural processing elements arranged D-dimensionally and divided into sub-sets 11. Each processing element in the sub-set has a bus 13 and it can communicate with one another. Each processing element is the member of one sub-set 11 in the respective dimensions. The respective processing elements in one sub-set 11 are connected in the sub-set by an output means. They transmit messages to the other processing elements in the pertinent sub-set. They have individual input means for the respective processing elements in the sub-set and they receive the messages from the other processing elements on the input stages. |
