发明名称 WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY
摘要 Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
申请公布号 US2016301548(A1) 申请公布日期 2016.10.13
申请号 US201615187382 申请日期 2016.06.20
申请人 Intel Corporation 发明人 Musah Tawfiq;Keskin Gokce;Balamurugan Ganesh;Jaussi James E.;Casper Bryan K.
分类号 H04L25/03;H04L7/00 主分类号 H04L25/03
代理机构 代理人
主权项
地址 Santa Clara CA US