Hardware-based time alignment of wireless links

摘要

For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

主权项

1. An article of manufacture comprising a baseband digital front-end (BDFE) processor for a multiple-in, multiple-out (MIMO) system having one or more radio-frequency integrated circuit (RFIC) chips connected to the BDFE processor by way of multiple JESD204B lanes, the BDFE processor comprising:
one or more sync-alignment circuits comprising one or more sets of integrated circuits that generate multiple, time-aligned JESD204B SYNC˜ signals for a group of the JESD204B lanes based on a sync-to-lane mapping and a lane-to-group mapping; and multiple idle generation circuits comprising multiple sets of the integrated circuits that generate multiple, time-aligned JESD204B IDLE signals for the group of the JESD204B lanes based on a group-to-idle mapping.