Program optimizing circuit and method for an electrically erasable and programmable semiconductor memory device

摘要

A program optimizing circuit for an EEPROM array comprising a program voltage generating circuit connected to each of bit lines, an anti-program voltage generating circuit connected between input/output data line and data input/output buffer and circuit for causing column decoder to selectively produce anti-program voltage or column address, is disclosed. The program voltage generating circuit further includes a first high voltage pumping circuit, transfer means and latch circuit. The operation of the first high voltage pumping circuit is controlled by the data stored in the latch circuit. In programming, the anti-program voltage is applied to all the bit lines, so as to prevent the unwanted memory cells from being programmed or erased.