STATIC EDGE-TRIGGERED D-FLIP-FLOP OF LOW POWER CONSUMPTION

摘要

PURPOSE: To reduce power consumption and allow a device to be compact. CONSTITUTION: The second inverter of a flip flop constituting a tristate gate and two inverters is constituted of four field effect supplementary pair transistors MP1 and MP2 and MN1 and MN2. The first supplementary pair of transistors MP2 and MN 2 have sources connected to one supply node and gates connected to the other supply node. The other supplementary pair of transistors have drains which are connected in common to the output node of the second inverter and gates connected to the output node of the first inverter, and it has a size which is substantially smaller than the size of the first supplementary transistor pair.