发明名称 GAME MACHINE
摘要 PROBLEM TO BE SOLVED: To prevent fraudulent control of input/output in a peripheral device constituting a game machine by permitting the control of the input/output corresponding to address data only when regular address data of full bits are used. SOLUTION: An address decoder includes input terminals for inputting address data of a prescribed number of bits and output terminals in the number smaller than the total number obtained by decoding the whole bit patterns of the address data of the prescribed number of bits. The address decoder also includes signal output determination circuits (gates 403c and 403d) for decoding address data A0-A3 necessary for addressing the output terminal outputting chip selection signals; and a gate circuit 403e for enabling the decoding operation of the signal output determination circuits only if the address data A4-A7 at the upper positions are within a prescribed address range when enable signals G1 and G2 are input. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009000131(A) 申请公布日期 2009.01.08
申请号 JP20070160821 申请日期 2007.06.19
申请人 DAITO GIKEN:KK 发明人 SUDO SHINGO
分类号 A63F5/04 主分类号 A63F5/04
代理机构 代理人
主权项
地址
您可能感兴趣的专利