Fixing of semiconductor hold time

摘要

Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.

主权项

1. A computer-implemented method for design analysis and modification comprising:
estimating hold-time requirements for a semiconductor design based on ideal clocks; allocating, using one or more processors, placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design; wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and modifying the design by performing hold-time fixing on the design.