System level simulation in network on chip architecture

摘要

Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

主权项

1. A method, comprising:
performing, on a computer, a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transactions comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent; and generating subsequent messages in the sequence of the one or more messages for ones of the plurality of transactions based on a first message destination node in the sequence of the one or more messages, wherein the subsequent messages are generated at each destination node of the one or more messages.