Modular cell for a memory array, the modular cell including a memory circuit and a read circuit

摘要

A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for example, a floating gate transistor) coupled to an RS flip flop. The RS flip flop is configured with a p-channel transistor coupled to receive a first enable signal and an n-channel transistor coupled to receive a second enable signal. The assertion of the enable signals is offset in time to control operations for forcing latch nodes to a specific voltage and enabling latching operation. The read circuit includes latch circuit coupled to outputs of the RS flip flop and operable as a sense amplifier circuit. The memory and read circuits are fabricated within a rectangular circuit area. Many such rectangular circuit area may be positioned adjacent to each other in a row or column of the memory array.

主权项

1. A memory cell, comprising:
a memory circuit, comprising:
a first floating gate transistor coupled between a source line and a first latch node;a second floating gate transistor coupled between the source line and a second latch node;a first true data input line;a second complementary data input line; anda reset/set (RS) flip flop circuit having a set input coupled to the first true data input line, a reset input coupled to the second complementary data input line, a true output and a complement output, and further including at least one n-channel transistor having a gate terminal driven by a first enable signal and at least one p-channel transistor having a gate terminal driven by a second enable signal; wherein during a read mode of operation for the memory cell said first and second enable signals are not simultaneously asserted; and wherein during a write mode of operation for the memory cell said first and second enable signals are simultaneously asserted.