| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a delay stage and a delay circuit which are insensitive to operational power supply voltage and have nearly constant delay time, regardless of the time intervals between pulses of an input signal. <P>SOLUTION: The delay stage comprises a first inverter which inverts and outputs an input signal; a first capacitor, one end of which is connected to a first voltage node; a first switch, which is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on responding to a control signal; a second inverter which inverts and outputs an output signal of the first inverter; a second capacitor, one end of which is connected to a second voltage node; and a second switch which is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on responding to the inverted signal of the control signal. The transition of the control signal is generated, before transition of the input signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
