发明名称 |
METHOD AND APPARATUS FOR CLOCK CYCLE STEALING |
摘要 |
A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
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申请公布号 |
US2009063888(A1) |
申请公布日期 |
2009.03.05 |
申请号 |
US20070841179 |
申请日期 |
2007.08.31 |
申请人 |
GOLD SPENCER M;KWAN BILL K C;EATON CRAIG D |
发明人 |
GOLD SPENCER M.;KWAN BILL K.C.;EATON CRAIG D. |
分类号 |
G06F1/06 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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