发明名称 |
Phase and frequency locked clock generator |
摘要 |
A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.
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申请公布号 |
US6166606(A) |
申请公布日期 |
2000.12.26 |
申请号 |
US19990247896 |
申请日期 |
1999.02.10 |
申请人 |
ZILOG, INC. |
发明人 |
TSYRGANOVICH, ANATOLIY V. |
分类号 |
G09G3/20;H03L7/07;H03L7/085;H04N5/06;H04N5/12;H04N5/445;(IPC1-7):H03L7/06 |
主分类号 |
G09G3/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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