| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock regeneration circuit capable of lowering the jitter of a clock component of a symbol so that a clock can be regenerated stably without increasing the Q of a band filter when a signal modulated by a QPSK modulation system or eight-phase PSK modulation system is demodulated. <P>SOLUTION: An input QPSK modulated wave signal is passed through a quadrature demodulator 1, roll-off filters 2a and 2b, and a delay detector 3 and the phase thereof is rotated by π/4 in a π/4 phase rotation circuit 4. A signal output from an adder 40 in the π/4 phase rotation circuit 4 passes through two zero points during one symbol before converging to a zero point. Since the output signal from the adder 40 is converted by a discrimination unit 5 into a binary waveform using the zero point as a threshold value, a waveform where jitter is suppressed can be obtained. A regenerative clock in which jitter is suppressed can be obtained from a PLL circuit 6 operating as a band filter. In recent years, eye of the eye pattern of a modulated I signal or Q signal is becoming narrower, and a clock with much jitter is generated when an output signal is converted into a binary waveform using the zero point as a threshold value, but that problem can be solved. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
