| 摘要 |
An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Zn, Jn) into a first part (msb(Zn), msb(Jn)) that is the power of 2 immediately lower or equal to the input signal and a second part (Zn-msb(Zn), Jn-msb(J<n>)) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X,Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X,Y) is calculated.
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