发明名称 Phase locked loop, phase detecting method for the phase locked loop, and receiver using the same
摘要 A Phase Locked Loop (PLL) is provided for improving acquisition performance in an acquisition state, while preventing performance degradation in a steady state under a low SNR environment, during phase detection, a phase detecting method for the PLL, and a receiver using the same. The PLL determines a period to which an input signal belongs according to the input signal and a feedback signal, outputs an error signal corresponding to the input signal by using a formula (or algorithm) set for the determined period, oscillates a predetermined frequency signal according to the error signal, and feeds back the oscillated signal.
申请公布号 US2006284690(A1) 申请公布日期 2006.12.21
申请号 US20060453852 申请日期 2006.06.16
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 ROH HEE-JIN;YOON SU-JIN;KIM MIN-GOO
分类号 H03L7/00 主分类号 H03L7/00
代理机构 代理人
主权项
地址